Make LPC1768 pinmapping not specific to Re-ARM (#8063)
* Merging early because of build failures. See #8105 * Make LPC1768 pinmapping not specific to Re-ARM * Add HAL_PIN_TYPE and LPC1768 pin features * M43 Updates * Move pin map into pinsDebug_LPC1768.h * Incorporate comments and M226 * Fix persistent store compilation issues * Update pin features * Update MKS SBASE pins * Use native LPC1768 pin numbers in M42, M43, and M2262.0.x
Thomas Moore
7 years ago
committed by
Roxy-3D
parent
e4266d0fde
commit
9e699811d2
@ -0,0 +1,509 @@
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/**
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* Marlin 3D Printer Firmware
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* Copyright (C) 2017 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
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*
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* Based on Sprinter and grbl.
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* Copyright (C) 2011 Camiel Gubbels / Erik van der Zalm
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/**
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* The class Servo uses the PWM class to implement its functions
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*
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* All PWMs use the same repetition rate - 20mS because that's the normal servo rate
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*/
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/**
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* This is a hybrid system.
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*
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* The PWM1 module is used to directly control the Servo 0, 1 & 3 pins. This keeps
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* the pulse width jitter to under a microsecond.
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*
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* For all other pins the PWM1 module is used to generate interrupts. The ISR
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* routine does the actual setting/clearing of pins. The upside is that any pin can
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* have a PWM channel assigned to it. The downside is that there is more pulse width
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* jitter. The jitter depends on what else is happening in the system and what ISRs
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* prempt the PWM ISR. Writing to the SD card can add 20 microseconds to the pulse
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* width.
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*/
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/**
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* The data structures are setup to minimize the computation done by the ISR which
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* minimizes ISR execution time. Execution times are 2.2 - 3.7 microseconds.
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*
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* Two tables are used. active_table is used by the ISR. Changes to the table are
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* are done by copying the active_table into the work_table, updating the work_table
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* and then swapping the two tables. Swapping is done by manipulating pointers.
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*
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* Immediately after the swap the ISR uses the work_table until the start of the
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* next 20mS cycle. During this transition the "work_table" is actually the table
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* that was being used before the swap. The "active_table" contains the data that
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* will start being used at the start of the next 20mS period. This keeps the pins
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* well behaved during the transition.
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*
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* The ISR's priority is set to the maximum otherwise other ISRs can cause considerable
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* jitter in the PWM high time.
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*
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* See the end of this file for details on the hardware/firmware interaction
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*/
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#ifdef TARGET_LPC1768
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#include <lpc17xx_pinsel.h>
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#include "LPC1768_PWM.h"
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#include "arduino.h"
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#define NUM_PWMS 6
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typedef struct { // holds all data needed to control/init one of the PWM channels
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uint8_t sequence; // 0: available slot, 1 - 6: PWM channel assigned to that slot
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pin_t pin;
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uint16_t PWM_mask; // MASK TO CHECK/WRITE THE IR REGISTER
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volatile uint32_t* set_register;
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volatile uint32_t* clr_register;
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uint32_t write_mask; // USED BY SET/CLEAR COMMANDS
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uint32_t microseconds; // value written to MR register
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uint32_t min; // lower value limit checked by WRITE routine before writing to the MR register
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uint32_t max; // upper value limit checked by WRITE routine before writing to the MR register
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bool PWM_flag; // 0 - USED BY sERVO, 1 - USED BY ANALOGWRITE
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uint8_t servo_index; // 0 - MAX_SERVO -1 : servo index, 0xFF : PWM channel
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bool active_flag; // THIS TABLE ENTRY IS ACTIVELY TOGGLING A PIN
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uint8_t assigned_MR; // Which MR (1-6) is used by this logical channel
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uint32_t PCR_bit; // PCR register bit to enable PWM1 control of this pin
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uint32_t PINSEL3_bits; // PINSEL3 register bits to set pin mode to PWM1 control
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} PWM_map;
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#define MICRO_MAX 0xffffffff
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#define PWM_MAP_INIT_ROW {0, 0xff, 0, 0, 0, 0, MICRO_MAX, 0, 0, 0, 0, 0, 0, 0, 0}
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#define PWM_MAP_INIT {PWM_MAP_INIT_ROW,\
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PWM_MAP_INIT_ROW,\
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PWM_MAP_INIT_ROW,\
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PWM_MAP_INIT_ROW,\
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PWM_MAP_INIT_ROW,\
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PWM_MAP_INIT_ROW,\
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};
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PWM_map PWM1_map_A[NUM_PWMS] = PWM_MAP_INIT;
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PWM_map PWM1_map_B[NUM_PWMS] = PWM_MAP_INIT;
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PWM_map *active_table = PWM1_map_A;
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PWM_map *work_table = PWM1_map_B;
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PWM_map *ISR_table;
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#define IR_BIT(p) (p >= 0 && p <= 3 ? p : p + 4 )
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#define COPY_ACTIVE_TABLE for (uint8_t i = 0; i < 6 ; i++) work_table[i] = active_table[i]
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#define PIN_IS_INVERTED(p) 0 // place holder in case inverting PWM output is offered
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/**
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* Prescale register and MR0 register values
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*
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* 100MHz PCLK 50MHz PCLK 25MHz PCLK 12.5MHz PCLK
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* ----------------- ----------------- ----------------- -----------------
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* desired prescale MR0 prescale MR0 prescale MR0 prescale MR0 resolution
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* prescale register register register register register register register register in degrees
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* freq value value value value value value value value
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*
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* 8 11.5 159,999 5.25 159,999 2.13 159,999 0.5625 159,999 0.023
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* 4 24 79,999 11.5 79,999 5.25 79,999 2.125 79,999 0.045
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* 2 49 39,999 24 39,999 11.5 39,999 5.25 39,999 0.090
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* 1 99 19,999 49 19,999 24 19,999 11.5 19,999 0.180
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* 0.5 199 9,999 99 9,999 49 9,999 24 9,999 0.360
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* 0.25 399 4,999 199 4,999 99 4,999 49 4,999 0.720
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* 0.125 799 2,499 399 2,499 199 2,499 99 2,499 1.440
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*
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* The desired prescale frequency comes from an input in the range of 544 - 2400 microseconds and the
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* desire to just shift the input left or right as needed.
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*
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* A resolution of 0.2 degrees seems reasonable so a prescale frequency output of 1MHz is being used.
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* It also means we don't need to scale the input.
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*
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* The PCLK is set to 25MHz because that's the slowest one that gives whole numbers for prescale and
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* MR0 registers.
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*
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* Final settings:
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* PCLKSEL0: 0x0
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* PWM1PR: 0x018 (24)
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* PWM1MR0: 0x04E1F (19,999)
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*
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*/
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void LPC1768_PWM_init(void) {
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#define SBIT_CNTEN 0 // PWM1 counter & pre-scaler enable/disable
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#define SBIT_CNTRST 1 // reset counters to known state
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#define SBIT_PWMEN 3 // 1 - PWM, 0 - timer
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#define SBIT_PWMMR0R 1
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#define PCPWM1 6
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#define PCLK_PWM1 12
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LPC_SC->PCONP |= (1 << PCPWM1); // enable PWM1 controller (enabled on power up)
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LPC_SC->PCLKSEL0 &= ~(0x3 << PCLK_PWM1);
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LPC_SC->PCLKSEL0 |= (LPC_PWM1_PCLKSEL0 << PCLK_PWM1);
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LPC_PWM1->MR0 = LPC_PWM1_MR0; // TC resets every 19,999 + 1 cycles - sets PWM cycle(Ton+Toff) to 20 mS
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// MR0 must be set before TCR enables the PWM
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LPC_PWM1->TCR = _BV(SBIT_CNTEN) | _BV(SBIT_CNTRST)| _BV(SBIT_PWMEN);; // enable counters, reset counters, set mode to PWM
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LPC_PWM1->TCR &= ~(_BV(SBIT_CNTRST)); // take counters out of reset
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LPC_PWM1->PR = LPC_PWM1_PR;
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LPC_PWM1->MCR = (_BV(SBIT_PWMMR0R) | _BV(0)); // Reset TC if it matches MR0, disable all interrupts except for MR0
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LPC_PWM1->CTCR = 0; // disable counter mode (enable PWM mode)
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LPC_PWM1->LER = 0x07F; // Set the latch Enable Bits to load the new Match Values for MR0 - MR6
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// Set all PWMs to single edge
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LPC_PWM1->PCR = 0; // single edge mode for all channels, PWM1 control of outputs off
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NVIC_EnableIRQ(PWM1_IRQn); // Enable interrupt handler
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// NVIC_SetPriority(PWM1_IRQn, NVIC_EncodePriority(0, 10, 0)); // normal priority for PWM module
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NVIC_SetPriority(PWM1_IRQn, NVIC_EncodePriority(0, 0, 0)); // minimizes jitter due to higher priority ISRs
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}
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bool PWM_table_swap = false; // flag to tell the ISR that the tables have been swapped
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bool PWM_MR0_wait = false; // flag to ensure don't delay MR0 interrupt
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bool LPC1768_PWM_attach_pin(pin_t pin, uint32_t min /* = 1 */, uint32_t max /* = (LPC_PWM1_MR0 - MR0_MARGIN) */, uint8_t servo_index /* = 0xff */) {
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while (PWM_table_swap) delay(5); // don't do anything until the previous change has been implemented by the ISR
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COPY_ACTIVE_TABLE; // copy active table into work table
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uint8_t slot = 0;
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for (uint8_t i = 0; i < NUM_PWMS ; i++) // see if already in table
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if (work_table[i].pin == pin) return 1;
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for (uint8_t i = 1; (i < NUM_PWMS + 1) && !slot; i++) // find empty slot
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if ( !(work_table[i - 1].set_register)) slot = i; // any item that can't be zero when active or just attached is OK
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if (!slot) return 0;
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slot--; // turn it into array index
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work_table[slot].pin = pin; // init slot
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work_table[slot].PWM_mask = 0; // real value set by PWM_write
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work_table[slot].set_register = PIN_IS_INVERTED(pin) ? &LPC_GPIO(LPC1768_PIN_PORT(pin))->FIOCLR : &LPC_GPIO(LPC1768_PIN_PORT(pin))->FIOSET;
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work_table[slot].clr_register = PIN_IS_INVERTED(pin) ? &LPC_GPIO(LPC1768_PIN_PORT(pin))->FIOSET : &LPC_GPIO(LPC1768_PIN_PORT(pin))->FIOCLR;
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work_table[slot].write_mask = LPC_PIN(LPC1768_PIN_PIN(pin));
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work_table[slot].microseconds = MICRO_MAX;
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work_table[slot].min = min;
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work_table[slot].max = MIN(max, LPC_PWM1_MR0 - MR0_MARGIN);
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work_table[slot].servo_index = servo_index;
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work_table[slot].active_flag = false;
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//swap tables
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PWM_MR0_wait = true;
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while (PWM_MR0_wait) delay(5); //wait until MR0 interrupt has happend so don't delay it.
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NVIC_DisableIRQ(PWM1_IRQn);
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PWM_map *pointer_swap = active_table;
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active_table = work_table;
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work_table = pointer_swap;
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PWM_table_swap = true; // tell the ISR that the tables have been swapped
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NVIC_EnableIRQ(PWM1_IRQn); // re-enable PWM interrupts
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return 1;
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}
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#define pin_11_PWM_channel 2
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#define pin_6_PWM_channel 3
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#define pin_4_PWM_channel 1
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// used to keep track of which Match Registers have been used and if they will be used by the
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// PWM1 module to directly control the pin or will be used to generate an interrupt
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typedef struct { // status of PWM1 channel
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uint8_t map_used; // 0 - this MR register not used/assigned
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uint8_t map_PWM_INT; // 0 - available for interrupts, 1 - in use by PWM
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pin_t map_PWM_PIN; // pin for this PwM1 controlled pin / port
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volatile uint32_t* MR_register; // address of the MR register for this PWM1 channel
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uint32_t PCR_bit; // PCR register bit to enable PWM1 control of this pin
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uint32_t PINSEL3_bits; // PINSEL3 register bits to set pin mode to PWM1 control
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} MR_map;
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MR_map map_MR[NUM_PWMS];
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void LPC1768_PWM_update_map_MR(void) {
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map_MR[0] = {0, (uint8_t) (LPC_PWM1->PCR & _BV(8 + pin_4_PWM_channel) ? 1 : 0), 4, &LPC_PWM1->MR1, 0, 0};
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map_MR[1] = {0, (uint8_t) (LPC_PWM1->PCR & _BV(8 + pin_11_PWM_channel) ? 1 : 0), 11, &LPC_PWM1->MR2, 0, 0};
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map_MR[2] = {0, (uint8_t) (LPC_PWM1->PCR & _BV(8 + pin_6_PWM_channel) ? 1 : 0), 6, &LPC_PWM1->MR3, 0, 0};
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map_MR[3] = {0, 0, 0, &LPC_PWM1->MR4, 0, 0};
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map_MR[4] = {0, 0, 0, &LPC_PWM1->MR5, 0, 0};
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map_MR[5] = {0, 0, 0, &LPC_PWM1->MR6, 0, 0};
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}
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uint32_t LPC1768_PWM_interrupt_mask = 1;
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void LPC1768_PWM_update(void) {
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for (uint8_t i = NUM_PWMS; --i;) { // (bubble) sort table by microseconds
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bool didSwap = false;
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PWM_map temp;
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for (uint16_t j = 0; j < i; ++j) {
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if (work_table[j].microseconds > work_table[j + 1].microseconds) {
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temp = work_table[j + 1];
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work_table[j + 1] = work_table[j];
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work_table[j] = temp;
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didSwap = true;
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}
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}
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if (!didSwap) break;
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}
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LPC1768_PWM_interrupt_mask = 0; // set match registers to new values, build IRQ mask
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for (uint8_t i = 0; i < NUM_PWMS; i++) {
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if (work_table[i].active_flag == true) {
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work_table[i].sequence = i + 1;
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// first see if there is a PWM1 controlled pin for this entry
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bool found = false;
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for (uint8_t j = 0; (j < NUM_PWMS) && !found; j++) {
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if ( (map_MR[j].map_PWM_PIN == work_table[i].pin) && map_MR[j].map_PWM_INT ) {
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*map_MR[j].MR_register = work_table[i].microseconds; // found one of the PWM pins
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work_table[i].PWM_mask = 0;
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work_table[i].PCR_bit = map_MR[j].PCR_bit; // PCR register bit to enable PWM1 control of this pin
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work_table[i].PINSEL3_bits = map_MR[j].PINSEL3_bits; // PINSEL3 register bits to set pin mode to PWM1 control} MR_map;
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map_MR[j].map_used = 2;
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work_table[i].assigned_MR = j +1; // only used to help in debugging
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found = true;
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}
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}
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// didn't find a PWM1 pin so get an interrupt
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for (uint8_t k = 0; (k < NUM_PWMS) && !found; k++) {
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if ( !(map_MR[k].map_PWM_INT || map_MR[k].map_used)) {
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*map_MR[k].MR_register = work_table[i].microseconds; // found one for an interrupt pin
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map_MR[k].map_used = 1;
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LPC1768_PWM_interrupt_mask |= _BV(3 * (k + 1)); // set bit in the MCR to enable this MR to generate an interrupt
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work_table[i].PWM_mask = _BV(IR_BIT(k + 1)); // bit in the IR that will go active when this MR generates an interrupt
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work_table[i].assigned_MR = k +1; // only used to help in debugging
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found = true;
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}
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}
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}
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else
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work_table[i].sequence = 0;
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}
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LPC1768_PWM_interrupt_mask |= (uint32_t) _BV(0); // add in MR0 interrupt
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// swap tables
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PWM_MR0_wait = true;
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while (PWM_MR0_wait) delay(5); //wait until MR0 interrupt has happend so don't delay it.
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NVIC_DisableIRQ(PWM1_IRQn);
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LPC_PWM1->LER = 0x07E; // Set the latch Enable Bits to load the new Match Values for MR1 - MR6
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PWM_map *pointer_swap = active_table;
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active_table = work_table;
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work_table = pointer_swap;
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PWM_table_swap = true; // tell the ISR that the tables have been swapped
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NVIC_EnableIRQ(PWM1_IRQn); // re-enable PWM interrupts
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}
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bool LPC1768_PWM_write(pin_t pin, uint32_t value) {
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while (PWM_table_swap) delay(5); // don't do anything until the previous change has been implemented by the ISR
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COPY_ACTIVE_TABLE; // copy active table into work table
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uint8_t slot = 0xFF;
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for (uint8_t i = 0; i < NUM_PWMS; i++) // find slot
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if (work_table[i].pin == pin) slot = i;
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if (slot == 0xFF) return false; // return error if pin not found
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LPC1768_PWM_update_map_MR();
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switch(pin) {
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case P1_20: // Servo 0, PWM1 channel 2 (Pin 11 P1.20 PWM1.2)
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map_MR[pin_11_PWM_channel - 1].PCR_bit = _BV(8 + pin_11_PWM_channel); // enable PWM1 module control of this pin
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map_MR[pin_11_PWM_channel - 1].map_PWM_INT = 1; // 0 - available for interrupts, 1 - in use by PWM
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map_MR[pin_11_PWM_channel - 1].PINSEL3_bits = 0x2 << 8; // ISR must do this AFTER setting PCR
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break;
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case P1_21: // Servo 1, PWM1 channel 3 (Pin 6 P1.21 PWM1.3)
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map_MR[pin_6_PWM_channel - 1].PCR_bit = _BV(8 + pin_6_PWM_channel); // enable PWM1 module control of this pin
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map_MR[pin_6_PWM_channel - 1].map_PWM_INT = 1; // 0 - available for interrupts, 1 - in use by PWM
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map_MR[pin_6_PWM_channel - 1].PINSEL3_bits = 0x2 << 10; // ISR must do this AFTER setting PCR
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break;
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case P1_18: // Servo 3, PWM1 channel 1 (Pin 4 P1.18 PWM1.1)
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map_MR[pin_4_PWM_channel - 1].PCR_bit = _BV(8 + pin_4_PWM_channel); // enable PWM1 module control of this pin
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map_MR[pin_4_PWM_channel - 1].map_PWM_INT = 1; // 0 - available for interrupts, 1 - in use by PWM
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map_MR[pin_4_PWM_channel - 1].PINSEL3_bits = 0x2 << 4; // ISR must do this AFTER setting PCR
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break;
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default: // ISR pins
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pinMode(pin, OUTPUT); // set pin to output but don't write anything in case it's already in use
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break;
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}
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work_table[slot].microseconds = MAX(MIN(value, work_table[slot].max), work_table[slot].min);
|
||||
work_table[slot].active_flag = true;
|
||||
|
||||
LPC1768_PWM_update();
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
bool LPC1768_PWM_detach_pin(pin_t pin) {
|
||||
while (PWM_table_swap) delay(5); // don't do anything until the previous change has been implemented by the ISR
|
||||
COPY_ACTIVE_TABLE; // copy active table into work table
|
||||
uint8_t slot = 0xFF;
|
||||
for (uint8_t i = 0; i < NUM_PWMS; i++) // find slot
|
||||
if (work_table[i].pin == pin) slot = i;
|
||||
if (slot == 0xFF) return false; // return error if pin not found
|
||||
|
||||
LPC1768_PWM_update_map_MR();
|
||||
|
||||
// OK to make these changes before the MR0 interrupt
|
||||
switch(pin) {
|
||||
case P1_20: // Servo 0, PWM1 channel 2 (Pin 11 P1.20 PWM1.2)
|
||||
LPC_PWM1->PCR &= ~(_BV(8 + pin_11_PWM_channel)); // disable PWM1 module control of this pin
|
||||
map_MR[pin_11_PWM_channel - 1].PCR_bit = 0;
|
||||
LPC_PINCON->PINSEL3 &= ~(0x3 << 8); // return pin to general purpose I/O
|
||||
map_MR[pin_11_PWM_channel - 1].PINSEL3_bits = 0;
|
||||
map_MR[pin_11_PWM_channel - 1].map_PWM_INT = 0; // 0 - available for interrupts, 1 - in use by PWM
|
||||
break;
|
||||
case P1_21: // Servo 1, PWM1 channel 3 (Pin 6 P1.21 PWM1.3)
|
||||
LPC_PWM1->PCR &= ~(_BV(8 + pin_6_PWM_channel)); // disable PWM1 module control of this pin
|
||||
map_MR[pin_6_PWM_channel - 1].PCR_bit = 0;
|
||||
LPC_PINCON->PINSEL3 &= ~(0x3 << 10); // return pin to general purpose I/O
|
||||
map_MR[pin_6_PWM_channel - 1].PINSEL3_bits = 0;
|
||||
map_MR[pin_6_PWM_channel - 1].map_PWM_INT = 0; // 0 - available for interrupts, 1 - in use by PWM
|
||||
break;
|
||||
case P1_18: // Servo 3, PWM1 channel 1 (Pin 4 P1.18 PWM1.1)
|
||||
LPC_PWM1->PCR &= ~(_BV(8 + pin_4_PWM_channel)); // disable PWM1 module control of this pin
|
||||
map_MR[pin_4_PWM_channel - 1].PCR_bit = 0;
|
||||
LPC_PINCON->PINSEL3 &= ~(0x3 << 4); // return pin to general purpose I/O
|
||||
map_MR[pin_4_PWM_channel - 1].PINSEL3_bits = 0;
|
||||
map_MR[pin_4_PWM_channel - 1].map_PWM_INT = 0; // 0 - available for interrupts, 1 - in use by PWM
|
||||
break;
|
||||
}
|
||||
|
||||
pinMode(pin, INPUT);
|
||||
|
||||
work_table[slot] = PWM_MAP_INIT_ROW;
|
||||
|
||||
LPC1768_PWM_update();
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
bool useable_hardware_PWM(pin_t pin) {
|
||||
COPY_ACTIVE_TABLE; // copy active table into work table
|
||||
for (uint8_t i = 0; i < NUM_PWMS; i++) // see if it's already setup
|
||||
if (work_table[i].pin == pin && work_table[i].sequence) return true;
|
||||
for (uint8_t i = 0; i < NUM_PWMS; i++) // see if there is an empty slot
|
||||
if (!work_table[i].sequence) return true;
|
||||
return false; // only get here if neither the above are true
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#define HAL_PWM_LPC1768_ISR extern "C" void PWM1_IRQHandler(void)
|
||||
|
||||
|
||||
// Both loops could be terminated when the last active channel is found but that would
|
||||
// result in variations ISR run time which results in variations in pulse width
|
||||
|
||||
/**
|
||||
* Changes to PINSEL3, PCR and MCR are only done during the MR0 interrupt otherwise
|
||||
* the wrong pin may be toggled or even have the system hang.
|
||||
*/
|
||||
|
||||
|
||||
HAL_PWM_LPC1768_ISR {
|
||||
if (PWM_table_swap) ISR_table = work_table; // use old table if a swap was just done
|
||||
else ISR_table = active_table;
|
||||
|
||||
if (LPC_PWM1->IR & 0x1) { // MR0 interrupt
|
||||
ISR_table = active_table; // MR0 means new values could have been loaded so set everything
|
||||
if (PWM_table_swap) LPC_PWM1->MCR = LPC1768_PWM_interrupt_mask; // enable new PWM individual channel interrupts
|
||||
|
||||
for (uint8_t i = 0; i < NUM_PWMS; i++) {
|
||||
if(ISR_table[i].active_flag && !((ISR_table[i].pin == P1_20) ||
|
||||
(ISR_table[i].pin == P1_21) ||
|
||||
(ISR_table[i].pin == P1_18)))
|
||||
*ISR_table[i].set_register = ISR_table[i].write_mask; // set pins for all enabled interrupt channels active
|
||||
if (PWM_table_swap && ISR_table[i].PCR_bit) {
|
||||
LPC_PWM1->PCR |= ISR_table[i].PCR_bit; // enable PWM1 module control of this pin
|
||||
LPC_PINCON->PINSEL3 |= ISR_table[i].PINSEL3_bits; // set pin mode to PWM1 control - must be done after PCR
|
||||
}
|
||||
}
|
||||
PWM_table_swap = false;
|
||||
PWM_MR0_wait = false;
|
||||
LPC_PWM1->IR = 0x01; // clear the MR0 interrupt flag bit
|
||||
}
|
||||
else {
|
||||
for (uint8_t i = 0; i < NUM_PWMS ; i++)
|
||||
if (ISR_table[i].active_flag && (LPC_PWM1->IR & ISR_table[i].PWM_mask) ){
|
||||
LPC_PWM1->IR = ISR_table[i].PWM_mask; // clear the interrupt flag bits for expected interrupts
|
||||
*ISR_table[i].clr_register = ISR_table[i].write_mask; // set channel to inactive
|
||||
}
|
||||
}
|
||||
|
||||
LPC_PWM1->IR = 0x70F; // guarantees all interrupt flags are cleared which, if there is an unexpected
|
||||
// PWM interrupt, will keep the ISR from hanging which will crash the controller
|
||||
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
/////////////////////////////////////////////////////////////////
|
||||
///////////////// HARDWARE FIRMWARE INTERACTION ////////////////
|
||||
/////////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* Almost all changes to the hardware registers must be coordinated with the Match Register 0 (MR0)
|
||||
* interrupt. The only exception is detaching pins. It doesn't matter when they go
|
||||
* tristate.
|
||||
*
|
||||
* The LPC1768_PWM_init routine kicks off the MR0 interrupt. This interrupt is never disabled or
|
||||
* delayed.
|
||||
*
|
||||
* The PWM_table_swap flag is set when the firmware has swapped in an updated table. It is
|
||||
* cleared by the ISR during the MR0 interrupt as it completes the swap and accompanying updates.
|
||||
* It serves two purposes:
|
||||
* 1) Tells the ISR that the tables have been swapped
|
||||
* 2) Keeps the firmware from starting a new update until the previous one has been completed.
|
||||
*
|
||||
* The PWM_MR0_wait flag is set when the firmware is ready to swap in an updated table and cleared by
|
||||
* the ISR during the MR0 interrupt. It is used to avoid delaying the MR0 interrupt when swapping in
|
||||
* an updated table. This avoids glitches in pulse width and/or repetition rate.
|
||||
*
|
||||
* The sequence of events during a write to a PWM channel is:
|
||||
* 1) Waits until PWM_table_swap flag is false before starting
|
||||
* 2) Copies the active table into the work table
|
||||
* 3) Updates the work table
|
||||
* NOTES - MR1-MR6 are updated at this time. The updates aren't put into use until the first
|
||||
* MR0 after the LER register has been written. The LER register is written during the
|
||||
* table swap process.
|
||||
* - The MCR mask is created at this time. It is not used until the ISR writes the MCR
|
||||
* during the MR0 interrupt in the table swap process.
|
||||
* 4) Sets the PWM_MR0_wait flag
|
||||
* 5) ISR clears the PWM_MR0_wait flag during the next MR0 interrupt
|
||||
* 6) Once the PWM_MR0_wait flag is cleared then the firmware:
|
||||
* disables the ISR interrupt
|
||||
* swaps the pointers to the tables
|
||||
* writes to the LER register
|
||||
* sets the PWM_table_swap flag active
|
||||
* re-enables the ISR
|
||||
* 7) On the next interrupt the ISR changes its pointer to the work table which is now the old,
|
||||
* unmodified, active table.
|
||||
* 8) On the next MR0 interrupt the ISR:
|
||||
* switches over to the active table
|
||||
* clears the PWM_table_swap and PWM_MR0_wait flags
|
||||
* updates the MCR register with the possibly new interrupt sources/assignments
|
||||
* writes to the PCR register to enable the direct control of the Servo 0, 1 & 3 pins by the PWM1 module
|
||||
* sets the PINSEL3 register to function/mode 0x2 for the Servo 0, 1 & 3 pins
|
||||
* NOTE - PCR must be set before PINSEL
|
||||
* sets the pins controlled by the ISR to their active states
|
||||
*/
|
||||
|
||||
@ -1,464 +0,0 @@
|
||||
/**
|
||||
* Marlin 3D Printer Firmware
|
||||
* Copyright (C) 2016 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
|
||||
*
|
||||
* Based on Sprinter and grbl.
|
||||
* Copyright (C) 2011 Camiel Gubbels / Erik van der Zalm
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __PINMAP_RE_ARM_H__
|
||||
#define __PINMAP_RE_ARM_H__
|
||||
|
||||
// ******************
|
||||
// Runtime pinmapping
|
||||
// ******************
|
||||
|
||||
#if SERIAL_PORT == 0
|
||||
#define NUM_ANALOG_INPUTS 6
|
||||
#else
|
||||
#define NUM_ANALOG_INPUTS 8
|
||||
#endif
|
||||
|
||||
const adc_pin_data adc_pin_map[] = {
|
||||
{0, 23, 0}, //A0 (T0) - D67 - TEMP_0_PIN
|
||||
{0, 24, 1}, //A1 (T1) - D68 - TEMP_BED_PIN
|
||||
{0, 25, 2}, //A2 (T2) - D69 - TEMP_1_PIN
|
||||
{0, 26, 3}, //A3 - D63
|
||||
{1, 30, 4}, //A4 - D37 - BUZZER_PIN
|
||||
{1, 31, 5}, //A5 - D49 - SD_DETECT_PIN
|
||||
#if SERIAL_PORT != 0
|
||||
{0, 3, 6}, //A6 - D0 - RXD0
|
||||
{0, 2, 7} //A7 - D1 - TXD0
|
||||
#endif
|
||||
};
|
||||
|
||||
constexpr FORCE_INLINE int8_t analogInputToDigitalPin(int8_t p) {
|
||||
return (p == 0 ? 67:
|
||||
p == 1 ? 68:
|
||||
p == 2 ? 69:
|
||||
p == 3 ? 63:
|
||||
p == 4 ? 37:
|
||||
p == 5 ? 49:
|
||||
#if SERIAL_PORT != 0
|
||||
p == 6 ? 0:
|
||||
p == 7 ? 1:
|
||||
#endif
|
||||
-1);
|
||||
}
|
||||
|
||||
constexpr FORCE_INLINE int8_t DIGITAL_PIN_TO_ANALOG_PIN(int8_t p) {
|
||||
return (p == 67 ? 0:
|
||||
p == 68 ? 1:
|
||||
p == 69 ? 2:
|
||||
p == 63 ? 3:
|
||||
p == 37 ? 4:
|
||||
p == 49 ? 5:
|
||||
#if SERIAL_PORT != 0
|
||||
p == 0 ? 6:
|
||||
p == 1 ? 7:
|
||||
#endif
|
||||
-1);
|
||||
}
|
||||
|
||||
#define NUM_DIGITAL_PINS 84
|
||||
|
||||
#define VALID_PIN(r) (r < 0 ? 0 :\
|
||||
r == 7 ? 0 :\
|
||||
r == 17 ? 0 :\
|
||||
r == 22 ? 0 :\
|
||||
r == 23 ? 0 :\
|
||||
r == 25 ? 0 :\
|
||||
r == 27 ? 0 :\
|
||||
r == 29 ? 0 :\
|
||||
r == 32 ? 0 :\
|
||||
r == 39 ? 0 :\
|
||||
r == 40 ? 0 :\
|
||||
r == 42 ? 0 :\
|
||||
r == 43 ? 0 :\
|
||||
r == 44 ? 0 :\
|
||||
r == 45 ? 0 :\
|
||||
r == 47 ? 0 :\
|
||||
r == 64 ? 0 :\
|
||||
r == 65 ? 0 :\
|
||||
r == 66 ? 0 :\
|
||||
r >= NUM_DIGITAL_PINS ? 0 : 1)
|
||||
|
||||
#define PWM_PIN(r) (r < 0 ? 0 :\
|
||||
r == 3 ? 1 :\
|
||||
r == 4 ? 1 :\
|
||||
r == 6 ? 1 :\
|
||||
r == 9 ? 1 :\
|
||||
r == 10 ? 1 :\
|
||||
r == 11 ? 1 :\
|
||||
r == 14 ? 1 :\
|
||||
r == 26 ? 1 :\
|
||||
r == 46 ? 1 :\
|
||||
r == 53 ? 1 :\
|
||||
r == 54 ? 1 :\
|
||||
r == 60 ? 1 : 0)
|
||||
|
||||
#define NUM_INTERRUPT_PINS 35
|
||||
|
||||
#define INTERRUPT_PIN(r) ( r< 0 ? 0 :\
|
||||
r == 0 ? 1 :\
|
||||
r == 1 ? 1 :\
|
||||
r == 8 ? 1 :\
|
||||
r == 9 ? 1 :\
|
||||
r == 10 ? 1 :\
|
||||
r == 12 ? 1 :\
|
||||
r == 16 ? 1 :\
|
||||
r == 20 ? 1 :\
|
||||
r == 21 ? 1 :\
|
||||
r == 24 ? 1 :\
|
||||
r == 25 ? 1 :\
|
||||
r == 26 ? 1 :\
|
||||
r == 28 ? 1 :\
|
||||
r == 34 ? 1 :\
|
||||
r == 35 ? 1 :\
|
||||
r == 36 ? 1 :\
|
||||
r == 38 ? 1 :\
|
||||
r == 46 ? 1 :\
|
||||
r == 48 ? 1 :\
|
||||
r == 50 ? 1 :\
|
||||
r == 51 ? 1 :\
|
||||
r == 52 ? 1 :\
|
||||
r == 54 ? 1 :\
|
||||
r == 55 ? 1 :\
|
||||
r == 56 ? 1 :\
|
||||
r == 57 ? 1 :\
|
||||
r == 58 ? 1 :\
|
||||
r == 59 ? 1 :\
|
||||
r == 60 ? 1 :\
|
||||
r == 61 ? 1 :\
|
||||
r == 62 ? 1 :\
|
||||
r == 63 ? 1 :\
|
||||
r == 67 ? 1 :\
|
||||
r == 68 ? 1 :\
|
||||
r == 69 ? 1 : 0)
|
||||
/*Internal SD Card */
|
||||
/*r == 80 ? 1 :\
|
||||
r == 81 ? 1 :\
|
||||
r == 82 ? 1 :\
|
||||
r == 83 ? 1 :\*/
|
||||
|
||||
const pin_data pin_map[] = { // pin map for variable pin function
|
||||
{0,3}, // DIO0 RXD0 A6 J4-4 AUX-1
|
||||
{0,2}, // DIO1 TXD0 A7 J4-5 AUX-1
|
||||
{1,25}, // DIO2 X_MAX_PIN 10K PULLUP TO 3.3v, 1K SERIES
|
||||
{1,24}, // DIO3 X_MIN_PIN 10K PULLUP TO 3.3v, 1K SERIES
|
||||
{1,18}, // DIO4 SERVO3_PIN FIL_RUNOUT_PIN 5V output, PWM
|
||||
{1,19}, // DIO5 SERVO2_PIN
|
||||
{1,21}, // DIO6 SERVO1_PIN J5-1
|
||||
{0xFF,0xFF}, // DIO7 N/C
|
||||
{2,7}, // DIO8 RAMPS_D8_PIN
|
||||
{2,4}, // DIO9 RAMPS_D9_PIN PWM
|
||||
{2,5}, // DIO10 RAMPS_D10_PIN PWM
|
||||
{1,20}, // DIO11 SERVO0_PIN
|
||||
{2,12}, // DIO12 PS_ON_PIN
|
||||
{4,28}, // DIO13 LED_PIN
|
||||
{1,26}, // DIO14 Y_MIN_PIN 10K PULLUP TO 3.3v, 1K SERIES
|
||||
{1,27}, // DIO15 Y_MAX_PIN 10K PULLUP TO 3.3v, 1K SERIES
|
||||
{0,16}, // DIO16 LCD_PINS_RS J3-7
|
||||
{0xFF,0xFF}, // DIO17 LCD_PINS_ENABLE MOSI_PIN(MOSI0) J3-10 AUX-3
|
||||
{1,29}, // DIO18 Z_MIN_PIN 10K PULLUP TO 3.3v, 1K SERIES
|
||||
{1,28}, // DIO19 Z_MAX_PIN 10K PULLUP TO 3.3v, 1K SERIES
|
||||
{0,0}, // DIO20 SCA
|
||||
{0,1}, // DIO21 SCL
|
||||
{0xFF,0xFF}, // DIO22 N/C
|
||||
{0xFF,0xFF}, // DIO23 LCD_PINS_D4 SCK_PIN(SCLK0) J3-9 AUX-3
|
||||
{0,4}, // DIO24 E0_ENABLE_PIN
|
||||
{0xFF,0xFF}, // DIO25 N/C
|
||||
{2,0}, // DIO26 E0_STEP_PIN
|
||||
{0xFF,0xFF}, // DIO27 N/C
|
||||
{0,5}, // DIO28 E0_DIR_PIN
|
||||
{0xFF,0xFF}, // DIO29 N/C
|
||||
{4,29}, // DIO30 E1_ENABLE_PIN
|
||||
{3,26}, // DIO31 BTN_EN1
|
||||
{0xFF,0xFF}, // DIO32 N/C
|
||||
{3,25}, // DIO33 BTN_EN2 J3-4
|
||||
{2,13}, // DIO34 E1_DIR_PIN
|
||||
{2,11}, // DIO35 BTN_ENC J3-3
|
||||
{2,8}, // DIO36 E1_STEP_PIN
|
||||
{1,30}, // DIO37 BEEPER_PIN A4 not 5V tolerant
|
||||
{0,10}, // DIO38 X_ENABLE_PIN
|
||||
{0xFF,0xFF}, // DIO39 N/C
|
||||
{0xFF,0xFF}, // DIO40 N/C
|
||||
{1,22}, // DIO41 KILL_PIN J5-4
|
||||
{0xFF,0xFF}, // DIO42 N/C
|
||||
{0xFF,0xFF}, // DIO43 N/C
|
||||
{0xFF,0xFF}, // DIO44 N/C
|
||||
{0xFF,0xFF}, // DIO45 N/C
|
||||
{2,3}, // DIO46 Z_STEP_PIN
|
||||
{0xFF,0xFF}, // DIO47 N/C
|
||||
{0,22}, // DIO48 Z_DIR_PIN
|
||||
{1,31}, // DIO49 SD_DETECT_PIN A5 J3-1 not 5V tolerant
|
||||
{0,17}, // DIO50 MISO_PIN(MISO0) AUX-3
|
||||
{0,18}, // DIO51 MOSI_PIN(MOSI0) LCD_PINS_ENABLE J3-10 AUX-3
|
||||
{0,15}, // DIO52 SCK_PIN(SCLK0) LCD_PINS_D4 J3-9 AUX-3
|
||||
{1,23}, // DIO53 SDSS(SSEL0) J3-5 AUX-3
|
||||
{2,1}, // DIO54 X_STEP_PIN
|
||||
{0,11}, // DIO55 X_DIR_PIN
|
||||
{0,19}, // DIO56 Y_ENABLE_PIN
|
||||
{0,27}, // DIO57 AUX-1 open collector
|
||||
{0,28}, // DIO58 AUX-1 open collector
|
||||
{2,6}, // DIO59 LCD_A0 J3-8 AUX-2
|
||||
{2,2}, // DIO60 Y_STEP_PIN
|
||||
{0,20}, // DIO61 Y_DIR_PIN
|
||||
{0,21}, // DIO62 Z_ENABLE_PIN
|
||||
{0,26}, // DIO63 AUX-2 A3 J5-3 AUX-2
|
||||
{0xFF,0xFF}, // DIO64 N/C
|
||||
{0xFF,0xFF}, // DIO65 N/C
|
||||
{0xFF,0xFF}, // DIO66 N/C
|
||||
{0,23}, // DIO67 TEMP_0_PIN A0
|
||||
{0,24}, // DIO68 TEMP_BED_PIN A1
|
||||
{0,25}, // DIO69 TEMP_1_PIN A2
|
||||
{1,16}, // DIO70 J12-3 ENET_MOC
|
||||
{1,17}, // DIO71 J12-4 ENET_MDIO
|
||||
{1,15}, // DIO72 J12-5 REF_CLK
|
||||
{1,14}, // DIO73 J12-6 ENET_RX_ER
|
||||
{1,9}, // DIO74 J12-7 ENET_RXD0
|
||||
{1,10}, // DIO75 J12-8 ENET_RXD1
|
||||
{1,8}, // DIO76 J12-9 ENET_CRS
|
||||
{1,4}, // DIO77 J12-10 ENET_TX_EN
|
||||
{1,0}, // DIO78 J12-11 ENET_TXD0
|
||||
{1,1}, // DIO79 J12-12 ENET_TXD1
|
||||
{0,14}, // DIO80 MKS-SBASE J7-6 & EXP1-5
|
||||
{0,7}, // DIO81 SD-SCK MKS-SBASE on board SD card and EXP2-2
|
||||
{0,8}, // DIO82 SD-MISO MKS-SBASE on board SD card and EXP2-1
|
||||
{0,9}, // DIO83 SD-MOSI MKS-SBASE n board SD card and EXP2-6
|
||||
// {0,6}, // DIO84 SD-CS on board SD card
|
||||
|
||||
};
|
||||
|
||||
// ***********************
|
||||
// Preprocessor pinmapping
|
||||
// ***********************
|
||||
|
||||
//#define RXD0 0 // A16 J4-4 AUX-1
|
||||
#define DIO0_PORT 0
|
||||
#define DIO0_PIN 3
|
||||
//#define TXD0 1 // A17 J4-5 AUX-1
|
||||
#define DIO1_PORT 0
|
||||
#define DIO1_PIN 2
|
||||
//#define X_MAX_PIN 2 // 10K PULLUP TO 3.3v, 1K SERIES
|
||||
#define DIO2_PORT 1
|
||||
#define DIO2_PIN 25
|
||||
//#define X_MIN_PIN 3 // 10K PULLUP TO 3.3v, 1K SERIES
|
||||
#define DIO3_PORT 1
|
||||
#define DIO3_PIN 24
|
||||
//#define SERVO3_PIN 4 // FIL_RUNOUT_PIN 5V output, PWM
|
||||
#define DIO4_PORT 1
|
||||
#define DIO4_PIN 18
|
||||
//#define SERVO2_PIN 5 //
|
||||
#define DIO5_PORT 1
|
||||
#define DIO5_PIN 19
|
||||
//#define SERVO1_PIN 6 // J5-1
|
||||
#define DIO6_PORT 1
|
||||
#define DIO6_PIN 21
|
||||
//#define RAMPS_D8_PIN 8 //
|
||||
#define DIO8_PORT 2
|
||||
#define DIO8_PIN 7
|
||||
//#define RAMPS_D9_PIN 9 // PWM
|
||||
#define DIO9_PORT 2
|
||||
#define DIO9_PIN 4
|
||||
//#define RAMPS_D10_PIN 10 // PWM
|
||||
#define DIO10_PORT 2
|
||||
#define DIO10_PIN 5
|
||||
//#define SERVO0_PIN 11 //
|
||||
#define DIO11_PORT 1
|
||||
#define DIO11_PIN 20
|
||||
//#define PS_ON_PIN 12 //
|
||||
#define DIO12_PORT 2
|
||||
#define DIO12_PIN 12
|
||||
//#define LED_PIN 13 //
|
||||
#define DIO13_PORT 4
|
||||
#define DIO13_PIN 28
|
||||
//#define Y_MIN_PIN 14 // 10K PULLUP TO 3.3v, 1K SERIES
|
||||
#define DIO14_PORT 1
|
||||
#define DIO14_PIN 26
|
||||
//#define Y_MAX_PIN 15 // 10K PULLUP TO 3.3v, 1K SERIES
|
||||
#define DIO15_PORT 1
|
||||
#define DIO15_PIN 27
|
||||
//#define LCD_PINS_RS 16 // J3-7
|
||||
#define DIO16_PORT 0
|
||||
#define DIO16_PIN 16
|
||||
//#define Z_MIN_PIN 18 // 10K PULLUP TO 3.3v, 1K SERIES
|
||||
#define DIO18_PORT 1
|
||||
#define DIO18_PIN 29
|
||||
//#define Z_MAX_PIN 19 // 10K PULLUP TO 3.3v, 1K SERIES
|
||||
#define DIO19_PORT 1
|
||||
#define DIO19_PIN 28
|
||||
//#define SCA 20 //
|
||||
#define DIO20_PORT 0
|
||||
#define DIO20_PIN 0
|
||||
//#define SCL 21 //
|
||||
#define DIO21_PORT 0
|
||||
#define DIO21_PIN 1
|
||||
//#define E0_ENABLE_PIN 24 //
|
||||
#define DIO24_PORT 0
|
||||
#define DIO24_PIN 4
|
||||
//#define E0_STEP_PIN 26 //
|
||||
#define DIO26_PORT 2
|
||||
#define DIO26_PIN 0
|
||||
//#define E0_DIR_PIN 28 //
|
||||
#define DIO28_PORT 0
|
||||
#define DIO28_PIN 5
|
||||
//#define E1_ENABLE_PIN 30 //
|
||||
#define DIO30_PORT 4
|
||||
#define DIO30_PIN 29
|
||||
//#define BTN_EN1 31 //
|
||||
#define DIO31_PORT 3
|
||||
#define DIO31_PIN 26
|
||||
//#define BTN_EN2 33 // J3-4
|
||||
#define DIO33_PORT 3
|
||||
#define DIO33_PIN 25
|
||||
//#define E1_DIR_PIN 34 //
|
||||
#define DIO34_PORT 2
|
||||
#define DIO34_PIN 13
|
||||
//#define BTN_ENC 35 // J3-3
|
||||
#define DIO35_PORT 2
|
||||
#define DIO35_PIN 11
|
||||
//#define E1_STEP_PIN 36 //
|
||||
#define DIO36_PORT 2
|
||||
#define DIO36_PIN 8
|
||||
//#define BEEPER_PIN 37 // A18 not 5V tolerant
|
||||
#define DIO37_PORT 1
|
||||
#define DIO37_PIN 30
|
||||
//#define X_ENABLE_PIN 38 //
|
||||
#define DIO38_PORT 0
|
||||
#define DIO38_PIN 10
|
||||
//#define KILL_PIN 41 // J5-4
|
||||
#define DIO41_PORT 1
|
||||
#define DIO41_PIN 22
|
||||
//#define Z_STEP_PIN 46 //
|
||||
#define DIO46_PORT 2
|
||||
#define DIO46_PIN 3
|
||||
//#define Z_DIR_PIN 48 //
|
||||
#define DIO48_PORT 0
|
||||
#define DIO48_PIN 22
|
||||
//#define SD_DETECT_PIN 49 // A19 J3-1 not 5V tolerant
|
||||
#define DIO49_PORT 1
|
||||
#define DIO49_PIN 31
|
||||
//#define MISO_PIN(MISO0) 50 // AUX-3
|
||||
#define DIO50_PORT 0
|
||||
#define DIO50_PIN 17
|
||||
//#define MOSI_PIN(MOSI0) 51 // LCD_PINS_ENABLE J3-10 AUX-3
|
||||
#define DIO51_PORT 0
|
||||
#define DIO51_PIN 18
|
||||
//#define SCK_PIN(SCLK0) 52 // LCD_PINS_D4 J3-9 AUX-3
|
||||
#define DIO52_PORT 0
|
||||
#define DIO52_PIN 15
|
||||
//#define SDSS(SSEL0) 53 // J3-5 AUX-3
|
||||
#define DIO53_PORT 1
|
||||
#define DIO53_PIN 23
|
||||
//#define X_STEP_PIN 54 //
|
||||
#define DIO54_PORT 2
|
||||
#define DIO54_PIN 1
|
||||
//#define X_DIR_PIN 55 //
|
||||
#define DIO55_PORT 0
|
||||
#define DIO55_PIN 11
|
||||
//#define Y_ENABLE_PIN 56 //
|
||||
#define DIO56_PORT 0
|
||||
#define DIO56_PIN 19
|
||||
//#define AUX-1 57 // open collector
|
||||
#define DIO57_PORT 0
|
||||
#define DIO57_PIN 27
|
||||
//#define AUX-1 58 // open collector
|
||||
#define DIO58_PORT 0
|
||||
#define DIO58_PIN 28
|
||||
//#define LCD_A0 59 // J3-8 AUX-2
|
||||
#define DIO59_PORT 2
|
||||
#define DIO59_PIN 6
|
||||
//#define Y_STEP_PIN 60 //
|
||||
#define DIO60_PORT 2
|
||||
#define DIO60_PIN 2
|
||||
//#define Y_DIR_PIN 61 //
|
||||
#define DIO61_PORT 0
|
||||
#define DIO61_PIN 20
|
||||
//#define Z_ENABLE_PIN 62 //
|
||||
#define DIO62_PORT 0
|
||||
#define DIO62_PIN 21
|
||||
//#define AUX-2 63 // A9 J5-3 AUX-2
|
||||
#define DIO63_PORT 0
|
||||
#define DIO63_PIN 26
|
||||
//#define TEMP_0_PIN 67 // A13
|
||||
#define DIO67_PORT 0
|
||||
#define DIO67_PIN 23
|
||||
//#define TEMP_BED_PIN 68 // A14
|
||||
#define DIO68_PORT 0
|
||||
#define DIO68_PIN 24
|
||||
//#define TEMP_1_PIN 69 // A15
|
||||
#define DIO69_PORT 0
|
||||
#define DIO69_PIN 25
|
||||
//#define J12-3 70 // ENET_MOC
|
||||
#define DIO70_PORT 1
|
||||
#define DIO70_PIN 16
|
||||
//#define J12-4 71 // ENET_MDIO
|
||||
#define DIO71_PORT 1
|
||||
#define DIO71_PIN 17
|
||||
//#define J12-5 72 // REF_CLK
|
||||
#define DIO72_PORT 1
|
||||
#define DIO72_PIN 15
|
||||
//#define J12-6 73 // ENET_RX_ER
|
||||
#define DIO73_PORT 1
|
||||
#define DIO73_PIN 14
|
||||
//#define J12-7 74 // ENET_RXD0
|
||||
#define DIO74_PORT 1
|
||||
#define DIO74_PIN 9
|
||||
//#define J12-8 75 // ENET_RXD1
|
||||
#define DIO75_PORT 1
|
||||
#define DIO75_PIN 10
|
||||
//#define J12-9 76 // ENET_CRS
|
||||
#define DIO76_PORT 1
|
||||
#define DIO76_PIN 8
|
||||
//#define J12-10 77 // ENET_TX_EN
|
||||
#define DIO77_PORT 1
|
||||
#define DIO77_PIN 4
|
||||
//#define J12-11 78 // ENET_TXD0
|
||||
#define DIO78_PORT 1
|
||||
#define DIO78_PIN 0
|
||||
//#define J12-12 79 // ENET_TXD1
|
||||
#define DIO79_PORT 1
|
||||
#define DIO79_PIN 1
|
||||
//#define J7-6 80 // MKS-SBASE J7-6
|
||||
#define DIO80_PORT 0
|
||||
#define DIO80_PIN 14
|
||||
//#define EXP2-2 81 // MKS-SBASE on board SD card and EXP2
|
||||
#define DIO81_PORT 0
|
||||
#define DIO81_PIN 7
|
||||
//#define EXP2-1 82 // MKS-SBASE on board SD card and EXP2
|
||||
#define DIO82_PORT 0
|
||||
#define DIO82_PIN 8
|
||||
//#define EXP2-6 83 // MKS-SBASE on board SD card and EXP2
|
||||
#define DIO83_PORT 0
|
||||
#define DIO83_PIN 9
|
||||
/**
|
||||
//#define SD-CS 81 // on board SD card
|
||||
#define DIO81_PORT 0
|
||||
#define DIO81_PIN 6
|
||||
//#define SD-SCK 82 // on board SD card
|
||||
#define DIO82_PORT 0
|
||||
#define DIO82_PIN 7
|
||||
//#define SD-MISO 83 // on board SD card
|
||||
#define DIO83_PORT 0
|
||||
#define DIO83_PIN 8
|
||||
//#define SD-MOSI 84 // on board SD card
|
||||
#define DIO84_PORT 0
|
||||
#define DIO84_PIN 9
|
||||
*/
|
||||
|
||||
#endif //__PINMAP_RE_ARM_H__
|
||||
@ -0,0 +1,50 @@
|
||||
/**
|
||||
* Marlin 3D Printer Firmware
|
||||
* Copyright (C) 2016 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
|
||||
*
|
||||
* Based on Sprinter and grbl.
|
||||
* Copyright (C) 2011 Camiel Gubbels / Erik van der Zalm
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifdef TARGET_LPC1768
|
||||
|
||||
#include "../../inc/MarlinConfig.h"
|
||||
#include "../../gcode/parser.h"
|
||||
|
||||
int16_t GET_PIN_MAP_INDEX(pin_t pin) {
|
||||
const uint8_t pin_port = LPC1768_PIN_PORT(pin),
|
||||
pin_pin = LPC1768_PIN_PIN(pin);
|
||||
for (size_t i = 0; i < NUM_DIGITAL_PINS; ++i)
|
||||
if (LPC1768_PIN_PORT(pin_map[i]) == pin_port && LPC1768_PIN_PIN(pin_map[i]) == pin_pin)
|
||||
return i;
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
int16_t PARSED_PIN_INDEX(char code, int16_t dval) {
|
||||
if (parser.seenval(code)) {
|
||||
int port, pin;
|
||||
if (sscanf(parser.strval(code), "%d.%d", &port, &pin) == 2)
|
||||
for (size_t i = 0; i < NUM_DIGITAL_PINS; ++i)
|
||||
if (LPC1768_PIN_PORT(pin_map[i]) == port && LPC1768_PIN_PIN(pin_map[i]) == pin)
|
||||
return i;
|
||||
}
|
||||
|
||||
return dval;
|
||||
}
|
||||
|
||||
#endif // TARGET_LPC1768
|
||||
Loading…
Reference in New Issue