Various fixes for DUE... (#10152)
- Watchdog reset during SD Card initialization. - Move `DebugMonitor` to `DebugMonitor_Due.cpp`. - Since the watchdog is enabled on boot do extra resets during init. - Have `thermalManager` do watchdog reset before its ISR starts to prevent reset. - Ensure that timers are stopped before reprogramming them to address tone issues. - Improve SAM3XE reset when reflashed through the native port.2.0.x
Eduardo José Tagle
7 years ago
committed by
Scott Lahteine
parent
c3c264978f
commit
97e8a6ebd9
@ -0,0 +1,238 @@
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/**
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* Marlin 3D Printer Firmware
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* Copyright (C) 2016 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
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*
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* Based on Sprinter and grbl.
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* Copyright (C) 2011 Camiel Gubbels / Erik van der Zalm
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#ifdef ARDUINO_ARCH_SAM
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#include "../../inc/MarlinConfig.h"
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#include "../../Marlin.h"
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// Debug monitor that dumps to the Programming port all status when
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// an exception or WDT timeout happens - And then resets the board
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// All the Monitor routines must run with interrupts disabled and
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// under an ISR execution context. That is why we cannot reuse the
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// Serial interrupt routines or any C runtime, as we don't know the
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// state we are when running them
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// A SW memory barrier, to ensure GCC does not overoptimize loops
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#define sw_barrier() asm volatile("": : :"memory");
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// (re)initialize UART0 as a monitor output to 250000,n,8,1
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static void TXBegin(void) {
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// Disable UART interrupt in NVIC
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NVIC_DisableIRQ( UART_IRQn );
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// Disable clock
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pmc_disable_periph_clk( ID_UART );
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// Configure PMC
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pmc_enable_periph_clk( ID_UART );
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// Disable PDC channel
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UART->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS;
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// Reset and disable receiver and transmitter
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UART->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | UART_CR_TXDIS;
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// Configure mode: 8bit, No parity, 1 bit stop
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UART->UART_MR = UART_MR_CHMODE_NORMAL | US_MR_CHRL_8_BIT | US_MR_NBSTOP_1_BIT | UART_MR_PAR_NO;
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// Configure baudrate (asynchronous, no oversampling) to 250000 bauds
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UART->UART_BRGR = (SystemCoreClock / (250000 << 4));
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// Enable receiver and transmitter
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UART->UART_CR = UART_CR_RXEN | UART_CR_TXEN;
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}
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// Send character through UART with no interrupts
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static void TX(char c) {
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while (!(UART->UART_SR & UART_SR_TXRDY)) { WDT_Restart(WDT); sw_barrier(); };
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UART->UART_THR = c;
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}
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// Send String through UART
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static void TX(const char* s) {
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while (*s) {
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TX(*s++);
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}
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}
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static void TXDigit(uint32_t d) {
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if (d < 10) TX((char)(d+'0'));
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else if (d < 16) TX((char)(d+'A'-10));
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else TX('?');
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}
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// Send Hex number thru UART
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static void TXHex(uint32_t v) {
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TX("0x");
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for (int i=0; i<8; i++, v <<= 4) {
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TXDigit((v >> 28) & 0xF);
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}
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}
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/**
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* HardFaultHandler_C:
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* This is called from the HardFault_HandlerAsm with a pointer the Fault stack
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* as the parameter. We can then read the values from the stack and place them
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* into local variables for ease of reading.
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* We then read the various Fault Status and Address Registers to help decode
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* cause of the fault.
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* The function ends with a BKPT instruction to force control back into the debugger
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*/
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extern "C"
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void HardFault_HandlerC(unsigned long *hardfault_args, unsigned long cause) {
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static const char* causestr[] = {
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"NMI","Hard","Mem","Bus","Usage","Debug","WDT","RSTC"
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};
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// Dump report to the Programming port (interrupts are DISABLED)
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TXBegin();
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TX("\n\n## Software Fault detected ##\n");
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TX("Cause: "); TX(causestr[cause]); TX('\n');
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TX("R0 : "); TXHex(((unsigned long)hardfault_args[0])); TX('\n');
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TX("R1 : "); TXHex(((unsigned long)hardfault_args[1])); TX('\n');
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TX("R2 : "); TXHex(((unsigned long)hardfault_args[2])); TX('\n');
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TX("R3 : "); TXHex(((unsigned long)hardfault_args[3])); TX('\n');
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TX("R12 : "); TXHex(((unsigned long)hardfault_args[4])); TX('\n');
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TX("LR : "); TXHex(((unsigned long)hardfault_args[5])); TX('\n');
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TX("PC : "); TXHex(((unsigned long)hardfault_args[6])); TX('\n');
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TX("PSR : "); TXHex(((unsigned long)hardfault_args[7])); TX('\n');
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// Configurable Fault Status Register
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// Consists of MMSR, BFSR and UFSR
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TX("CFSR : "); TXHex((*((volatile unsigned long *)(0xE000ED28)))); TX('\n');
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// Hard Fault Status Register
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TX("HFSR : "); TXHex((*((volatile unsigned long *)(0xE000ED2C)))); TX('\n');
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// Debug Fault Status Register
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TX("DFSR : "); TXHex((*((volatile unsigned long *)(0xE000ED30)))); TX('\n');
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// Auxiliary Fault Status Register
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TX("AFSR : "); TXHex((*((volatile unsigned long *)(0xE000ED3C)))); TX('\n');
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// Read the Fault Address Registers. These may not contain valid values.
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// Check BFARVALID/MMARVALID to see if they are valid values
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// MemManage Fault Address Register
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TX("MMAR : "); TXHex((*((volatile unsigned long *)(0xE000ED34)))); TX('\n');
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// Bus Fault Address Register
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TX("BFAR : "); TXHex((*((volatile unsigned long *)(0xE000ED38)))); TX('\n');
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// Reset controller
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NVIC_SystemReset();
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while(1) { WDT_Restart(WDT); }
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}
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__attribute__((naked)) void NMI_Handler(void) {
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__asm volatile (
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" tst lr, #4 \n"
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" ite eq \n"
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" mrseq r0, msp \n"
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" mrsne r0, psp \n"
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" mov r1,#0 \n"
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" b HardFault_HandlerC \n"
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);
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}
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__attribute__((naked)) void HardFault_Handler(void) {
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__asm volatile (
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" tst lr, #4 \n"
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" ite eq \n"
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" mrseq r0, msp \n"
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" mrsne r0, psp \n"
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" mov r1,#1 \n"
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" b HardFault_HandlerC \n"
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);
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}
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__attribute__((naked)) void MemManage_Handler(void) {
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__asm volatile (
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" tst lr, #4 \n"
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" ite eq \n"
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" mrseq r0, msp \n"
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" mrsne r0, psp \n"
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" mov r1,#2 \n"
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" b HardFault_HandlerC \n"
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);
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}
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__attribute__((naked)) void BusFault_Handler(void) {
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__asm volatile (
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" tst lr, #4 \n"
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" ite eq \n"
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" mrseq r0, msp \n"
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" mrsne r0, psp \n"
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" mov r1,#3 \n"
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" b HardFault_HandlerC \n"
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);
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}
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__attribute__((naked)) void UsageFault_Handler(void) {
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__asm volatile (
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" tst lr, #4 \n"
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" ite eq \n"
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" mrseq r0, msp \n"
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" mrsne r0, psp \n"
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" mov r1,#4 \n"
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" b HardFault_HandlerC \n"
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);
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}
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__attribute__((naked)) void DebugMon_Handler(void) {
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__asm volatile (
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" tst lr, #4 \n"
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" ite eq \n"
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" mrseq r0, msp \n"
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" mrsne r0, psp \n"
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" mov r1,#5 \n"
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" b HardFault_HandlerC \n"
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);
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}
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__attribute__((naked)) void WDT_Handler(void) {
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__asm volatile (
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" tst lr, #4 \n"
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" ite eq \n"
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" mrseq r0, msp \n"
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" mrsne r0, psp \n"
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" mov r1,#6 \n"
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" b HardFault_HandlerC \n"
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);
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}
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__attribute__((naked)) void RSTC_Handler(void) {
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__asm volatile (
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" tst lr, #4 \n"
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" ite eq \n"
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" mrseq r0, msp \n"
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" mrsne r0, psp \n"
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" mov r1,#7 \n"
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" b HardFault_HandlerC \n"
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);
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}
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#endif
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